fft_top Project Status (05/06/2012 - 20:35:17)
Project File: exp9_2.xise Parser Errors: No Errors
Module Name: fft_top Implementation State: Synthesized
Target Device: xc6slx9-3tqg144
  • Errors:
 No Errors
Product Version:ISE 13.2
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 1151 11440 10%
Number of Slice LUTs 959 5720 16%
Number of fully used LUT-FF pairs 909 1201 75%
Number of bonded IOBs 86 102 84%
Number of BUFG/BUFGCTRLs 1 16 6%
Number of DSP48A1s 4 16 25%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentΦάΘΥ ΞεΤΒ 6 20:35:16 2012006 Infos (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 05/06/2012 - 20:35:17